View MAX5650_4395344.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-3936; Rev 0; 2/06
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
General Description
The MAX5650/MAX5651/MAX5652 parallel-input, voltage-output, 16-bit, digital-to-analog converters (DACs) provide monotonic 16-bit output voltage over the full extended operating temperature range. The MAX5650/ MAX5651 include an internal precision low drift (10ppm/C) bandgap voltage reference, while the MAX5652 requires an external reference. The MAX5650 operates from a +5V single supply and has a +4.096V internal reference. The MAX5651 operates from either a +3V or +5V single supply and has a +2.048V internal reference. The MAX5652 operates from either a +3V or +5V single supply and accepts an input reference voltage between +2V and AV DD . TheMAX5650/MAX5651/ MAX5652 parallel inputs are double buffered and configurable as a single 16-bit wide input or a 2-byte input. The MAX5650/MAX5651/MAX5652 unbuffered DAC voltage output ranges from 0 to VREF. The MAX5650/MAX5651/MAX5652 feature an active-low hardware clear input (CLR) that clears the registers and the output to zero-scale (0000 hex) or midscale (8000 hex), depending on the state of the MID/ZERO input. These devices include matched scaling resistors for use with a precision external op amp (such as the MAX400) to generate a bipolar output-voltage swing. The MAX5650/MAX5651/MAX5652 are available in a 32pin, 5mm x 5mm TQFN package and are guaranteed over the extended temperature range (-40C to +85C). For 14-bit, pin-compatible versions of the MAX5650/ MAX5651/MAX5652, refer to the MAX5653/MAX5654/ MAX5655 datasheet. For 12-bit, pin-compatible versions of the MAX5650/ MAX5651/MAX5652, refer to the MAX5656/MAX5657/ MAX5658 datasheet. 16-Bit Resolution Parallel 16-Bit or 2-Byte Double Buffered Interface Guaranteed Monotonic Maximum INL: 4 LSB Fast 2s Settling Time Clear Input (CLR) Sets Output to Zero-Scale or Midscale Integrated Precision Resistors for Bipolar Operation Integrated Precision Bandgap Reference: +4.096V (MAX5650) +2.048V (MAX5651)
Features
MAX5650/MAX5651/MAX5652
Ordering Information
PART MAX5650ETJ MAX5651ETJ** MAX5652ETJ** PIN-PACKAGE 32 TQFN-EP* (5mm x 5mm) 32 TQFN-EP* (5mm x 5mm) 32 TQFN-EP* (5mm x 5mm) PACKAGE CODE T3255-4 T3255-4 T3255-4
Note: All devices specified over the -40C to +85C temperature range. *EP = Exposed paddle. Connect to AGND or leave unconnected. **Future product--contact factory for availability.
Functional Diagram
DVDD D15 8-BIT MSB INPUT REGISTER D8 D7 8-BIT LSB INPUT REGISTER D0 CSMSB WR CSLSB LDAC CLR POWER-ON RESET DGND MID/ZERO AGND GND 16-BIT DAC REGISTER BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY) R MTAP R INB AVDD REF INA
Applications
Automatic Test Equipment Process Control Digital Calibration Actuator Control Servo Loops Waveform Generators Motor Control
Selector Guide
PART MAX5650ETJ MAX5651ETJ MAX5652ETJ SUPPLY VOLTAGE (V) +4.75 to +5.25 +2.7 to +5.25 +2.7 to +5.25 REFERENCE (V) Internal, +4.096 Internal, +2.048 External INL (LSB, max) 4 -- --
16-BIT DAC
OUT
MAX5650 MAX5651 MAX5652
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
ABSOLUTE MAXIMUM RATINGS
AVDD to DVDD..............................................................6V AVDD to AGND, GND....................................... -0.3V to +6V DVDD to DGND............................................... -0.3V to +6V DGND to GND............................................. -0.3V to +0.3V DGND, GND to AGND................................... -0.3V to +0.3V D0-D15, CSLSB, CSMSB, WR, LDAC, CLR, MID/ZERO, to DGND.......................................-0.3V to (DVDD + 0.3V) REF to AGND.....................................-0.3V to (AVDD + 0.3V) OUT, MTAP, INA to AGND, GND...........................-0.3V to AVDD INB to AGND .....................................................-6V to +6V INB to MTAP......................................................-6V to +6V Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 32-Pin TQFN (derate 20.8mW/C above +70C)....2758.6mW Operating Temperature Range .......................-40C to +85C Storage Temperature Range.........................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5650
(AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL = , CL = 10pF, CREF = 1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Resolution Differential Nonlinearity Integral Nonlinearity Zero-Code Offset Error Zero-Code Temperature Coefficient Gain Error Gain-Error Temperature Coefficient DAC Output Resistance Bipolar Resistor Ratio Bipolar Resistor Ratio Error Bipolar Resistor Ratio Temperature Coefficient Bipolar Resistor Value Voltage Reference Reference Voltage Temperature Coefficient Reference Load Regulation Short-Circuit Current Reference Load Reference Power-Up Time Power-Supply Rejection Ratio PSRR IREF Settle to 0.5 LSB AVDD = DVDD = 4.75V to 5.25V (FS code) 4 0.5 VREF TCVREF VOUT / IOUT (Note 2) RINB and RINA (Note 4) TA = +25C (Note 2) 0 IOUT VREF / 10k 4.081 0.5 12.4 4.106 10 0.1 6 400 0.6 4.111 ROUT SYMBOL N DNL INL ZSE ZSTC (Note 2) (Note 3) (Note 2) (Note 4) RINB / RINA 0.1 6.2 1 0.05 0.05 10 Guaranteed monotonic CONDITIONS MIN 16 0.5 1 4 80 TYP MAX UNITS Bits LSB LSB V ppmFS/ C LSB ppm/C k / % ppm/C k V ppm/C V/A mA A ms mV/V
STATIC PERFORMANCE--ANALOG SECTION
VOLTAGE REFERENCE (RREF = 10k, CREF(MIN) = 1F)
2
_______________________________________________________________________________________
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX5650 (continued)
(AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL = , CL = 10pF, CREF = 1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Output Settling Time DAC Glitch Impulse Digital Feedthrough SYMBOL CONDITIONS 7F60H to 80A0H or 80A0H to 7F60H to 0.5 LSB Major carry transition Code = 0000 hex; CSLSB = CSMSB = DVDD, D0-D15 transition from 0 to DVDD Frequency = 0.1Hz to 10Hz Frequency = 10Hz to 1kHz For zero-scale to full-scale or full-scale to zero-scale transition VIH VIL IIN CIN AVDD DVDD IAVDD + IDVDD tCS tWR tCWS tCWH tDWS tDWH tLDAC tCLR (Note 9) All digital inputs at DVDD or 0V, AVDD = DVDD 4.75 AVDD 0.3 5 5.25 AVDD + 0.3 2 (Note 8) (Note 8) 2.4 0.8 1 MIN TYP 2 10 3 MAX UNITS s nV*s nV*s
MAX5650/MAX5651/MAX5652
DYNAMIC PERFORMANCE--ANALOG SECTION
DYNAMIC PERFORMANCE--VOLTAGE REFERENCE SECTION Noise Voltage (Note 6) VREF Glitch Impulse STATIC PERFORMANCE--DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance POWER SUPPLY Analog Supply Range Digital Supply Range Positive Supply Current V V mA V V A pF 15 12 10 VP-P VRMS nV*s
TIMING CHARACTERISTICS (Figure 4) CSMSB and CSLSB Pulse Width WR Pulse Width CSMSB or CSLSB to WR Setup Time CSMSB or CSLSB to WR Hold Time Data Valid to WR Setup Time Data Valid to WR Hold Time LDAC Pulse Width CLR Pulse Width 40 40 0 0 40 0 40 40 ns ns ns ns ns ns ns ns
Note 1: 100% production tested at TA = +25C and TA = +85C. Guaranteed by design at TA = -40C. Note 2: Temperature coefficient is determined by the box method in which the maximum change over the temperature range is divided by T. Note 3: Gain error is measured at the full-scale code and is calculated with respect to the reference voltage (REF). Note 4: Resistor tolerance is typically 20%. Note 5: Guaranteed by design, not production tested. Note 6: Noise is measured at the reference output. Note 7: Min/max range guaranteed by gain-error test. Operation outside min/max limits results in degraded performance. Note 8: The devices draw higher supply current when the digital inputs are driven between (DVDD - 0.5V) and (DGND + 0.5V). See Digital Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 9: For optimal performance AVDD = DVDD. _______________________________________________________________________________________ 3
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
Typical Operating Characteristics
(AVDD = DVDD = +5V, AGND = DGND = GND = 0V, RL = , CL = 10pF, CREF = 1F for the MAX5650/MAX5651, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5650 toc01
ZERO-CODE OFFSET ERROR vs. TEMPERATURE (MAX5650)
MAX5650 toc02
GAIN ERROR vs. TEMPERATURE (MAX5650)
MAX5650 toc03
1.0 +INL 0.5 INL (LSB)
25
2
20 OFFSET ERROR (V)
1 FS GAIN ERROR (LSB)
15
0
0
10
-1
-0.5 -INL -1.0 -40 -15 10 35 60 85 TEMPERATURE (C)
5
-2
0 -40 -15 10 35 60 85 TEMPERATURE (C)
-3 -40 -15 10 35 60 85 TEMPERATURE (C)
REFERENCE VOLTAGE vs. TEMPERATURE (MAX5650)
MAX5650 toc04
REFERENCE-VOLTAGE NOISE (MAX5650)
f = 0.1Hz TO 10Hz
MAX5650 toc05
TOTAL SUPPLY CURRENT vs. TEMPERATURE (MAX5650)
MAX5650 toc06
4.100
1.2
REFERENCE VOLTAGE (V)
4.099
1.1 SUPPLY CURRENT (mA)
4.098 10V/div 4.097
1.0
0.9
4.096
0.8 CODE = FFFF
4.095 -40 -15 10 35 60 85 TEMPERATURE (C) 1s/div
0.7 -40 -15 10 35 60 85 TEMPERATURE (C)
REFERENCE VOLTAGE vs. DIGITAL INPUT CODE
MAX5650 toc07
DIGITAL SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE (MAX5650)
DIGITAL SUPPLY CURRENT (mA)
MAX5650 toc08
FULL-SCALE STEP RESPONSE (MAX5650)
MAX5650 toc09
4.09699 4.09698 REFERENCE VOLTAGE (V) 4.09697 4.09696 4.09695 4.09694 4.09693
100 10 1 0.1 0.01 0.001 ALL DIGITAL INPUTS CONNECTED TOGETHER AVDD = DVDD = 5.25V
D1 5V/div 0
VOUT 2V/div 0 CODE FFFF TO OOOO STEP 5 6 400ns/div
0.0001 0 10000 20000 30000 40000 50000 60000 70000 CODE 0.00001 0 1
2
3
4
DIGITAL INPUT VOLTAGE (V)
4
_______________________________________________________________________________________
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, AGND = DGND = GND = 0V, RL = , CL = 10pF, CREF = 1F for the MAX5650/MAX5651, TA = +25C, unless otherwise noted.)
FULL-SCALE STEP RESPONSE (MAX5650)
MAX5650 toc10
MAX5650/MAX5651/MAX5652
MAJOR-CARRY GLITCH
MAX5650 toc11
MAJOR-CARRY GLITCH
MAX5650 toc12
D1 5V/div 0V
D15 5V/div 0V VOUT 20mV/div 0V
D15 5V/div 0V VOUT 20mV/div 0V
VOUT 2V/div
0V CODE 0000 TO FFFF STEP 400ns/div
CODE 7FFF TO 8000 STEP 1s/div
CODE 8000 TO 7FFF STEP 1s/div
DIGITAL FEEDTHROUGH (MAX5650)
MAX5650 toc13
SMALL-SIGNAL SETTLING TIME
MAX5650 toc14
SMALL-SIGNAL SETTLING TIME
MAX5650 toc15
D1 5V/div
VOUT 10mV/div 0V
VOUT 10mV/div 0V
VOUT 20mV/div
FS TRANSITION 1s/div
CODE 0000 TO 00A2 STEP 400ns/div
CODE 00A2 TO 0000 STEP 400ns/div
REFERENCE BANDWIDTH (MAX5652)
MAX5650 toc16
REFERENCE FEEDTHROUGH (MAX5652)
VREF = 3.5V + 0.5VP-P -20 VOUT/VREF (dB) -40 -60 -80 CODE = 0000h
MAX5650 toc17
5 0 -5 -10 VOUT/VREF (dB) -15 -20 -25 -30 -35 -40 -45 -50 10 100 1000 CODE = FFFFh VREF = 3.5V + 0.5VP-P
0
-100 -120 10,000 0.01 0.1 1 10 100 1000 10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
_______________________________________________________________________________________
5
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DGND DVDD CSLSB CSMSB Data Input Bit 0 (LSB) Data Input Bit 1 Data Input Bit 2 Data Input Bit 3 Data Input Bit 4 Data Input Bit 5 Data Input Bit 6 Data Input Bit 7 Data Input Bit 8 Data Input Bit 9 Data Input Bit 10 Data Input Bit 11 Data Input Bit 12 Data Input Bit 13 Data Input Bit 14 Data Input Bit 15 (MSB) Digital Ground Digital Supply. Bypass DVDD to DGND with a 0.1F capacitor as close to the device as possible. Lower 8-Bit Active-Low Chip Select. When CSLSB is driven low the data inputs D0-D7 are loaded to the input and DAC registers depending on the state of WR and LDAC (see Table 1). Upper 8-Bit Active-Low Chip Select. When CSMSB is driven low the data inputs D8-D15 are loaded to the input and DAC registers depending on the state of WR and LDAC (see Table 1). Active-Low Write Input. While chip select (CSLSB and/or CSMSB) is low, the data on D0-D7 and/or D8-D15 is presented to the input register when WR is low. A rising edge on WR then latches the data to the input register (see Table 1). Hold WR low to make the input register transparent. Asynchronous Active-Low Load DAC Input. When LDAC is low, the data in the input register is presented to the DAC register. A rising edge on LDAC then latches the data to the DAC register (see Table 1). Hold WR and LDAC low to perform a write-through operation. Asynchronous Active-Low Clear DAC Input. Pull CLR low to clear the input and DAC registers and set the DAC output to midscale (8000 hex), if MID/ZERO is high, or zero scale (0000 hex), if MID/ZERO is low. Midscale/Zero-Scale Clear Output Value Select. Pull MID/ZERO low for zero-scale clear output (0000 hex) or high for midscale clear output (8000 hex). Internal Scaling Resistor Midpoint Tap. Connect to the inverting input of an external op amp. Internal Resistor Input B. Free end of internal resistor (RINB). Connect to the output of an external output buffer for bipolar operation. Analog Supply. Bypass AVDD to AGND with a 0.1F capacitor as close to the device as possible. Analog Ground Internal Resistor Input A. Free end of internal resistor (RINA). Connect to REF for bipolar operation. FUNCTION
21
WR
22
LDAC
23
CLR
24 25 26 27 28 29
MID/ZERO MTAP INB AVDD AGND INA
6
_______________________________________________________________________________________
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
Pin Description (continued)
PIN NAME FUNCTION Internal Reference Voltage Output (MAX5650/MAX5651). Connect a 1F < CREF < 47F between REF and AGND as close to the device as possible. The internal reference voltage of the MAX5650 is +4.096V and +2.048V for the MAX5651. External Reference Voltage Input (MAX5652). Connect to an external voltage reference source between +2V and AVDD. 31 32 -- OUT GND EP DAC Output DAC Ground Exposed paddle. Connect to AGND or leave unconnected.
MAX5650/MAX5651/MAX5652
30
REF
Typical Application Circuits
DVDD D15 8-BIT BUS 8-BIT MSB INPUT REGISTER D8 D7 8-BIT LSB INPUT REGISTER D0 CSMSB GND CONTROL LINES WR CSLSB LDAC CLR DGND POWER-ON RESET MID/ZERO AGND 16-BIT DAC REGISTER AVDD BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY) REF INA R MTAP R INB 16-BIT DAC OUT 0 TO VREF
C
MAX5650 MAX5651 MAX5652
Figure 1. Typical Application Circuit for C Byte-Wide Interface
_______________________________________________________________________________________
7
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
Typical Application Circuits (continued)
ACTUATOR DRIVE CIRCUIT DVDD AVDD REF INA
R D15 16-BIT BUS 8-BIT MSB INPUT REGISTER D8 D7 ASIC D0 CSMSB GND CONTROL LINES WR CSLSB LDAC CLR DGND POWER-ON RESET MID/ZERO AGND 8-BIT LSB INPUT REGISTER OUT 0 TO VREF 0 TO VREF 16-BIT DAC REGISTER BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY)
R INB MTAP +12V
16-BIT DAC
MAX5650 MAX5651 MAX5652
Figure 2. Typical Application Circuit for Unipolar Configuration
8
_______________________________________________________________________________________
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
Typical Application Circuits (continued)
MAX5650/MAX5651/MAX5652
DVDD
AVDD
REF
INA
R D15 8-BIT BUS 8-BIT MSB INPUT REGISTER D8 D7 FPGA D0 CSMSB GND CONTROL LINES WR CSLSB LDAC CLR DGND POWER-ON RESET MID/ZERO AGND 8-BIT LSB INPUT REGISTER OUT -5V 0 TO VREF +/- VREF 16-BIT DAC REGISTER BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY)
R INB MTAP +5V
16-BIT DAC
MAX5650 MAX5651 MAX5652
Figure 3. Typical Application Circuit for Bipolar Configuration
_______________________________________________________________________________________
9
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
tCS CSLSB tCS CSMSB tCWS tWR WR tCWH tCWS tWR tCWH
tLDAC LDAC tDWS tDWH D0-D15 VALID DATA VALID DATA tDWS tDWH
Figure 4. Timing Diagram
Detailed Description
The MAX5650/MAX5651/MAX5652 parallel-input, voltage-output DACs offer full 16-bit performance with less than 4 LSB integral nonlinearity and less than 1 LSB differential nonlinearity, ensuring monotonic performance over the full operating temperature range. The DAC is composed of an inverted R2R ladder with the unbuffered output available directly at OUT, allowing 16-bit performance from the reference voltage to the DAC ground (GND). The parallel inputs are doublebuffered and configurable as a single 16-bit wide input or a 2-byte input. The MAX5650/MAX5651 include internal precision low-drift (10ppm/C) bandgap voltage references of +4.096V and +2.048V, respectively. The MAX5652 accepts an external reference voltage between +2V and AVDD. The MAX5650 operates with a supply voltage range of +4.75V to +5.25V, while the MAX5651/MAX5652 operate with a supply voltage range of +2.7V to +5.25V. The MAX5652 accepts an external reference with a voltage range extending from +2V to AVDD. The output voltage of the DAC is determined as follows: VOUT = VREF x N / 65536 where N is the numeric value of the DAC's binary input code (0 to 65535) and VREF is the reference voltage. At a full-scale transition, the instantaneous charge demand from the external reference is about 550pC. For a reference with a 1F load capacitor, the charge demand causes an instantaneous reference voltage drop of 550V. A 10F load capacitor causes a voltage drop of 55V. This glitch recovers in a time inversely proportional to the bandwidth of the voltage reference, which should be sufficiently fast to recover before the next DAC transition to avoid accumulation of the glitch energy and a shift in the average reference voltage. For a +4.096V reference with 1F bypass capacitor, it takes three time constants to recover to 0.5 LSB accuracy. Therefore, a 96kHz bandwidth reference recovers in 5s while a 960kHz bandwidth reference recovers in 0.5s. For further voltage-reference selection assistance, visit www.maxim-ic.com/appnotes.cfm/appnote_number/754.
Voltage Reference
The MAX5650/MAX5651 provide a 10ppm/C (typ) internal precision bandgap voltage reference with a load regulation specification of less than 0.6V/A (maximum) over the entire operating temperature range. The reference voltage for the MAX5650 is +4.096V, while the reference voltage for the MAX5651 is +2.048V. Connect a capacitor ranging between 1F and 47F from REF to ground as close to the device as possible. Use a low-ESR ceramic capacitor such as the GRM series from Murata.
10
______________________________________________________________________________________
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
Digital Interface
The MAX5650/MAX5651/MAX5652 accept a single 16bit wide input or an 8 plus 8-bit wide input. Data latches or transfers directly to the DAC depending on the state of the control inputs CLR, CSLSB, CSMSB, LDAC, MID/ZERO, and WR. All digital inputs are compatible with both TTL and CMOS logic. The double buffered input consists of an input register and a DAC register (see the Functional Diagram). Data is loaded into the input register using CSLSB, CSMSB, and WR. The input register is transparent when WR and CSLSB and/or CSMSB are low. The rising edge of WR, while CSLSB is low, latches the lower byte (D0-D7) into the input register. The rising edge of WR, while CSMSB is low, latches the upper byte (D8-D15) into the input register. The sequence of loading the MSB and LSB does not matter. See Figure 1 for byte-wide interface circuit. The DAC register is transparent when LDAC is low. The rising edge of LDAC latches data into the DAC register. The DAC's analog output reflects the data held in the DAC register. Both the input register and DAC register are transparent when CSLSB, CSMSB, WR, and LDAC are driven low. In this case, any change at D0-D15 appears at the output instantly. See Table 1 for the truth table.
MAX5650/MAX5651/MAX5652
Table 1. Truth Table
CLR 1 1 1 1 1 1 CSLSB 0 0 1 1 X X CSMSB 1 1 0 0 X X 1 1 0 WR 0 LDAC 1 1 1 1 0 FUNCTION Loads least significant byte into the input register. DAC output remains unchanged. Latches least significant byte into the input register. DAC output remains unchanged. Loads most significant byte into the input register. DAC output remains unchanged. Latches most significant byte into the input register. DAC output remains unchanged. Transfers data from the input register into the DAC register and updates the DAC output. Latches data from the input register into the DAC register. DAC output remains unchanged. 0 1 0 1 0 0 1 X Most significant input and DAC registers are transparent. DAC output updates immediately with the most significant input data and least significant input register data. No operation. Both most significant and least significant input registers and DAC register are transparent. DAC output updates immediately with the most significant and least significant input data. Loads all 16 bits into the input register. DAC output remains unchanged. Least significant input and DAC registers are transparent. DAC output updates immediately with the least significant input data and most significant register data. Transfers data held in the input register to the DAC register and updates the DAC output. No operation. Sets the input and DAC registers and DAC output to midscale (if MID/ZERO = 1) or zero-scale (if MID/ZERO = 0).
1 1 1 1 1 1 1 0
1 X 0 0 0 1 1 X
0 X 0 0 1 1 1 X
0 1 0 0 0 X X X
0 = Low state. 1 = High state. X = Don't care. = Rising edge.
______________________________________________________________________________________
11
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
The MAX5650/MAX5651/MAX5652 provide an asynchronous clear input (CLR). Asserting CLR resets the input and DAC registers and DAC output to midscale if the MID/ZERO input is high and to zero scale when MID/ZERO is low. where D is the decimal value of the DACs binary input code. Table 3 shows digital codes and corresponding output voltages for bipolar operation.
Power-On Reset (POR)
The MAX5650/MAX5651/MAX5652 provide an internal POR circuit. On power-up, the input and DAC registers and DAC output are set to 0000 hex if MID/ZERO is low or 8000 hex if MID/ZERO is high. Wait 10s after power-up before pulling CSMSB or CSLSB low.
Table 2. Unipolar Code Table
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT, VOUT VREF x (65,535 / 65,536) VREF x (32,768 / 65,536) = 0.5VREF VREF x (1 / 65,536) 0V
Internal Scaling Resistors
The MAX5650/MAX5651/MAX5652 include two internal scaling resistors of 12.4k (typ) each that are matched to 0.05% or better. Use these resistors with a precision external op amp to generate a bipolar output swing (see the Bipolar Operation section). The free ends of these resistors are accessible at INA and INB while the midpoint is accessible at MTAP. Connect INB to the output of the op amp and INA to REF for bipolar operation. Negative voltages are only allowed at INB (see the Absolute Maximum Ratings section).
Table 3. Bipolar Code Table
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 ANALOG OUTPUT, VOUT +VREF x (32,767 / 32,768) +VREF x (1 / 32,768) 0V -VREF (1 / 32,768) -VREF x (32,768 / 32,768) = -VREF
Applications Information
Unipolar Buffered/Unbuffered Operation
Unbuffered operation reduces power consumption as well as the offset error contributed by the external output buffer (see Figure 1). The R2R DAC output is available directly at OUT, allowing 16-bit performance from +VREF to GND without degradation at zero scale. The typical application circuit (Figure 2) shows the MAX5650/MAX5651/MAX5652 configured for a buffered unipolar voltage-output operation. Use the integrated precision matched resisters for op-amp input impedance matching. Table 2 shows digital codes and corresponding output voltages for unipolar buffered or unbuffered operation.
Power-Supply and Layout Considerations
Careful PC board layout is important for optimal system performance. Wire-wrapped boards, sockets, and breadboards are not recommended. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Connect AGND and DGND to the highest quality ground available. Star-connect all ground return paths back to AGND or use a multilayer board with a low-inductance ground plane. Connect analog and digital ground planes together at a lowimpedance power-supply source. For the MAX5652, keep the trace between the reference source to the reference input short and low impedance. Bypass each supply with a 0.1F capacitor as close as possible to the IC for optimal 16-bit performance.
Bipolar Operation
For bipolar voltage-output operation, use an external op amp (such as the MAX400) in conjunction with the internal scaling resistors (see Figure 3). Connect the free end of the internal resistor (INB) to the output of the external op amp and the free end of the other resistor (INA) to REF. Connect the midpoint of the resistors to the inverting input of the op amp. Connect the output of the DAC to the noninverting input of the external op amp. The resulting transfer function is as follows: VOUT = VREF [(2D / 65, 536) - 1]
Chip Information
PROCESS: BiCMOS
12
______________________________________________________________________________________
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference
Pin Configuration
MID/ZERO CSMSB CSLSB LDAC DVDD
MAX5650/MAX5651/MAX5652
CLR
24 MTAP 25 INB 26 AVDD 27 AGND 28 INA 29 REF 30 OUT 31 GND 32 + 1 D0
23
22
21
WR
TOP VIEW
20
19
18
17 16 15 14 D15 D14 D13 D12 D11 D10 D9 D8
MAX5650 MAX5651 MAX5652
DGND 13 12 11 10 9 8 D7
2 D1
3 D2
4 D3
5 D4
6 D5
7 D6
TQFN 5mm x 5mm
______________________________________________________________________________________
13
16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
D2 D D/2 MARKING k L
C L
b D2/2
0.10 M C A B
AAAAA
E/2 E2/2 E (NE-1) X e
C L
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1 2
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
L
MIN. NOM. MAX. MIN. NOM. MAX. 0.15
DOWN BONDS ALLOWED
A A1 A3 b D E e k L
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC.
- 0.25 - 0.25 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC L1
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products 2006 Printed USA is a registered trademark of Maxim Integrated Products. Inc.

▲Up To Search▲

Price & Availability of MAX5650

	To Download MAX5650 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .